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MC34844
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
Table 6. Write Registers
reg / db
00
D7
OVP3
D6
OVP2
D5
OVP1
D4
OVP0
D3
D2
NINEN
D1
PINEN
EN
D0
01
CLRI2C
SETI2C
04
05
06
FPWM5
FPWM11
FPWM17
FPWM4
FPWM10
FPWM16
FPWM3
FPWM9
FPWM15
FPWM2
FPWM8
FPWM14
FPWM1
FPWM7
FPWM13
FPWM0
FPWM6
FPWM12
07
DPWM7
DPWM6
DPWM5
DPWM4
DPWM3
DPWM2
DPWM1
DPWM0
08
CHEN4
CHEN3
CHEN2
CHEN1
CHEN0
09
STRB
CLRFAIL
ALL_OFF
CHEN9
CHEN8
CHEN7
CHEN6
CHEN5
14
BST1
BST0
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
ICH0_7
ICH1_7
ICH2_7
ICH3_7
ICH4_7
ICH5_7
ICH6_7
ICH7_7
ICH8_7
ICH9_7
ICHG_7
ICH0_6
ICH1_6
ICH2_6
ICH3_6
ICH4_6
ICH5_6
ICH6_6
ICH7_6
ICH8_6
ICH9_6
ICHG_6
ICH0_5
ICH1_5
ICH2_5
ICH3_5
ICH4_5
ICH5_5
ICH6_5
ICH7_5
ICH8_5
ICH9_5
ICHG_5
ICH0_4
ICH1_4
ICH2_4
ICH3_4
ICH4_4
ICH5_4
ICH6_4
ICH7_4
ICH8_4
ICH9_4
ICHG_4
ICH0_3
ICH1_3
ICH2_3
ICHG_3
ICH4_3
ICH5_3
ICH6_3
ICH7_3
ICH8_3
ICH9_3
ICHG_3
ICH0_2
ICH1_2
ICH2_2
ICH3_2
ICH4_2
ICH5_2
ICH6_2
ICH7_2
ICH8_2
ICH9_2
ICHG_2
ICH0_1
ICH1_1
ICH2_1
ICH3_1
ICH4_1
ICH5_1
ICH6_1
ICH7_1
ICH8_1
ICH9_1
ICHG_1
ICH0_0
ICH1_0
ICH2_0
ICH3_0
ICH4_0
ICH5_0
ICH6_0
ICH7_0
ICH8_0
ICH9_0
ICHG_0
Table 7. Register Description
Register Name
EN
PINEN
NINEN
OVP[3:0]
SETI2C
CLRI2C
FPWM[17:0]
DPWM[7:0]
CHEN[9:0]
ALL_OFF
CLRFAIL
STRB
Default Value
(Hex)
1
1
1
F
0
0
300
FF
3FF
0
0
0
Description
Chip Enable by software. This signal is ‘OR’ed with external EN (0=off, 1 =on)
PIN pin enable (0=off, 1 =on)
NIN pin enable (0=off, 1 =on)
OVP voltage
SET I 2 C communication (Disable SM Bus Mode)
Clear set I 2 C
PWM Frequency
PWM Duty Cycle (FFh =100%)
Channel Enable (0=off, 1=on)
All 10 channels OFF at the same. In order to reactivate channels this bit should be clear.
Clear fail if channels are re-enable.
Strobe MODE (0=Parallel, 1=Strobe)
34844
Analog Integrated Circuit Device Data
23
Freescale Semiconductor
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